The fabrication of various solid state devices requires the use of planar substrates, or semiconductor wafers, on which integrated circuits are fabricated. The final number, or yield, of functional integrated circuits on a wafer at the end of the IC fabrication process is of utmost importance to semiconductor manufacturers, and increasing the yield of circuits on the wafer is the main goal of semiconductor fabrication. After packaging, the circuits on the wafers are tested, wherein non-functional dies are marked using an inking process and the functional dies on the wafer are separated and sold. IC fabricators increase the yield of dies on a wafer by exploiting economies of scale. Over 1000 dies may be formed on a single wafer which measures from six to twelve inches in diameter.
Various processing steps are used to fabricate integrated circuits on a semiconductor wafer. These steps include deposition of a conducting layer on the silicon wafer substrate; formation of a photoresist or other mask such as titanium oxide or silicon oxide, in the form of the desired metal interconnection pattern, using standard lithographic or photolithographic techniques; subjecting the wafer substrate to a dry etching process to remove the conducting layer from the areas not covered by the mask, thereby etching the conducting layer in the form of the masked pattern on the substrate; removing or stripping the mask layer from the substrate typically using reactive plasma and chlorine gas, thereby exposing the top surface of the conductive interconnect layer; and cooling and drying the wafer substrate by applying water and nitrogen gas to the wafer substrate.
During the photolithography step of semiconductor production, light energy is applied through a reticle mask onto the photoresist material previously deposited on the wafer to define circuit patterns which will be etched in a subsequent processing step to define the circuits on the wafer. A reticle is a transparent plate patterned with a circuit image to be formed in the photoresist coating on the wafer. A reticle contains the circuit pattern image for only a few of the die on a wafer, such as four die, for example, and thus, must be stepped and repeated across the entire surface of the wafer. In contrast, a photomask, or mask, includes the circuit pattern image for all of the die on a wafer and requires only one exposure to transfer the circuit pattern image for all of the dies to the wafer.
The circuit features on a reticle must be precisely fabricated since these features are transferred to the wafer to define the pattern of the circuits to be fabricated on the wafer. Thus, the quality of the reticle is important to produce high-quality imaging during submicron photolithography. If circuit pattern defects such as distortion and incorrect image placement on the reticle are not detected prior to the exposure step, these defects will be reproduced in the resist on the wafer. For this reason, once they are fabricated reticles are typically subjected to extensive automated testing for defects and particles.
Reticles are used in stepper systems and in step-and-scan systems, or scanners, which use a reduction lens to reduce overlay accuracy during circuit patterning. Steppers typically operate under a reduction ratio of 5:1 or 4:1, whereas scanners typically operate under a reduction ratio of 4:1. The small field exposure size on steppers and scanners facilitates precise control of tolerances during reticle alignment.
Steppers and scanners typically include a computer-controlled automatic alignment system which is contained in a pre-alignment unit and identifies alignment marks on the reticle. The reticle is mounted in a reticle stage and the wafer is supported on a wafer chuck provided on a wafer stage. An illumination system projects light through the alignment marks on the reticle and onto the wafer surface, respectively. Light detectors then optically detect the alignment marks on the reticle and marks on the wafer that are illuminated by the light. Laser infraredometry is used to measure the position of the wafer stage that holds the wafer chuck. Once obtained, the position data is fed into the system computer with a software interface to the electromechanical system used to facilitate the adjustments needed to properly align the wafer to the reticle.
The pre-alignment unit and exposure chamber of a scanner or stepper are typically component parts of a track system in which multiple wafers are transferred among the various stations of a photolithography process. In the track interface which is adjacent to the pre-alignment unit, multiple wafers are temporarily delayed in a track buffer cassette prior to being sequentially transferred into the pre-alignment unit for proper alignment of each wafer preparatory to exposure.
Patterning of the circuit pattern on the photoresist is one of the main factors that dictates product success or failure, and a number of factors can contribute to pattern instability. For example, it has been found that a major source of pattern instability is heat which emanates from a large heat source (WEE lamp) inside the track interface. This heat raises the temperature of the wafers delayed in the buffer cassette on the order of 1˜2 degrees Celsius and causes the photoresist to expand, thus distorting the circuit pattern as it is transferrd from the reticle to the photoresist during exposure. Experiments have shown that with a fab temp. of 23.1 degrees Celsius, a track inteface temperature of 25 degrees Celsius, a track buffer cassette temperature of 25.5 degrees C and a scanner interior temperature of 23.0 degrees Celsius, adjustment of the track interface ventilation can control the temperature within approximately 0.5 degrees Celsius. However, it has been found that using such ventilation to control the track interface temperature is not workable because the track interface temperature ventilation uses air to facilitate cooling and this approach causes cooling temperature instability.
In further experiments, a wafer was coated with a bottom ARC (anti-reflective coating) layer, a middle layer of SEPR432 resist, and a top ARC layer in a diamond-shaped pattern having a length-to-width ratio of 30:1. In a first experiment, the wafer was delayed in a buffer cassette in the track interface of a scanner for 1 hour prior to exposure of the wafer. It was found that the pattern transferred from the reticle to the wafer during the first few wafer shots was seriously deformed and that the length of the pattern in middle shots differed. The pattern formed on the wafer in the last few shots was the same as the pattern defined in the reticle.
In a second experiment, a wafer was delayed outside the buffer cassette prior to exposure of the wafer. It was found that the pattern in the reticle and the pattern transferred to the photoresist on the wafer were the same. In a third experiment, the wafer was delayed in the cassette buffer, but in the pre-alignment unit, the wafer was sprayed with a gas having a temperature of 23 degrees C. In that case, the pattern in the reticle and the pattern transferred to the photoresist on the wafer were the same, as in the second experiment.
Accordingly, a pattern control system is needed which facilitates the cooling of wafers in a pre-alignment unit of a scanner or stepper prior to exposure of the wafers in order to preserve the integrity of a circuit pattern formed in a photoresist layer on the wafers.
An object of the present invention is to provide a novel pattern control system which enhances the quality of circuit pattern images formed on semiconductor wafers.
Another object of the present invention is to provide a novel pattern control system which ensures the integrity of a circuit pattern image photolithographically transferred from a reticle to a wafer.
Still another object of the present invention is to provide a novel pattern control system which prevents distorted circuit pattern images from being formed on a wafer during photolithography.
Yet another object of the present invention is to provide a novel pattern control system which enhances the yield of devices on a wafer.
A still further object of the present invention is to provide a novel pattern control system which may include a pre-alignment unit of a stepper or scanner and a source of cooling gas provided in fluid communication with the pre-alignment unit for cooling a wafer or wafers prior to photolithographic exposure.
Another object of the present invention is to provide a novel pattern control system which may utilize a gas distribution plate to disperse a cooling gas into thermal contact with a wafer to cool the wafer prior to photolithographic exposure.
Still another object of the present invention is to provide a novel pattern control system which may utilize a cooling fluid to cool a wafer chuck and a wafer resting on the chuck by conduction prior to photolithographic exposure of the wafer.
Yet another object of the present invention is to provide a novel method of enhancing the quality of circuit pattern images formed on a wafer during photolithography.